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8 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF080
Not Recommended for New Designs
Power-Up Specifications
All functionalities and DC specifications are specified for a V DD ramp rate of greater than 1V per 100
ms (0V to 1.8V in less than 180 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset
is required. The recommended V DD power-up to RESET# high time should be greater than 100 μs to
ensure a proper reset. See Table 11 and Figures 25 and 26 for more information.
Table 11: Recommended System Power-up Timings
Symbol
T PU-READ1
Parameter
V DD Min to Read Operation
Minimum
100
Units
μs
T PU-WRITE
1
V DD Min to Write Operation
100
μs
T11.0 25024
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T PU-READ
V DD
RESET#
0V
V DD min
V IH
T RECR
CE#
1203 F37.0
Note: See Table 2 on page 7 for T RECR parameter.
Figure 25: Power-Up Reset Diagram
V DD
V DD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
V DD Min
T PU-READ
T PU-WRITE
Device fully accessible
Time
1203 F27.0
Figure 26: Power-up Timing Diagram
?2012 Silicon Storage Technology, Inc.
26
DS25024B
03/12
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